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Foobar8568 21 hours ago [-]
> Engineering sample silicon for Agilex 27 FPGAs is expected in the second half of 2027.
That's not even a paper launch at this stage.
jacquesm 15 hours ago [-]
This is not software.
YakBizzarro 19 hours ago [-]
quite typical with FPGAs. Plus this is the general public announcement. Key customers likely already have samples since a while
Foobar8568 17 hours ago [-]
I would have expected that Engineering samples would be already available or soon, not in one year or more.
ksec 18 hours ago [-]
Can anyone comment on Altera since they have escaped from Intel ? And how it fares again Xilinx / AMD?
My old perception was still based on pre AMD Xilinx era from 4-5 years ago and Xilinx was basically winning 60-70% market shares as Intel Altera was no where near competitive. ( As usual with any Intel acquisition)
Aromasin 17 hours ago [-]
I worked there for 3 years, and still catch up with everyone from time to time at tradeshows and the occasional social. They definitely seem in much better spirits, but I'll be brutally honest, many of the people I knew that were the top talent have moved to AMD or Lattice. It's a lot of new faces last time I was there, from a mix of different companies (ADI, TI, Microchip, etc), so I guess time will tell whether some fresh bodies do something interesting.
They restricted wage growth too much for too long under Intel (despite being the only growing business unit), so the people with the valuable experience moved elsewhere. The Agilex line-up finally looks to be in the place it should have been 3 years ago, and it seems like they brought in a good marketing team following the Silverlake acquisition, but they still fall in this weird middle-ground now selling "performance-per-watt", which is a hard sell when most engineers optimise for the extremes. If I'm just need a bridge or some glue-logic, I don't need a device which will singe my thumbprints off while doing that. Generally, if you want better performance, AMD does an excellent job, or if you need low power consumption, Lattice is like 4 or 5x lower or more with just enough fmax and IO to be dangerous. If you look read Lattice's shareholder briefings, they're running away with the low/mid-range devices up to ~500k LUTs, and AMD is dominating anything 1M+. I couldn't help but laugh the other day when I saw an Intel reference design with a Lattice MachXO5-NX on it. Look at pretty much any datacentre rack now, and you'll spot 4-64 Lattice devices, when it used to be MAX10s top to bottom. Everything else is swept up by AMD.
For Altera, Agilex 9 (ADC and DAC converters integrated with an SoC FPGA) is probably their most interesting device, but that customer base is limited - basically comms and maybe radar with some weird and wonderful optical or quantum compute applications. I've heard friends of mine in the industry say very good things about it, but RF is not my strength so I can't comment.
In all honesty, they've got an insane fight on their hands to regain the market share. They canned their low end road-map when Sandra Riviera came in (as a classic Intel VP would do) and put all their eggs in the Agilex 7 basket for a long time. They've got Agilex 5 now (and Agilex 3, which is just the bottom SKUs of 5 with it painted over by marketing to fill the gap), which is great for vision applications, but only because they had a fantastic video and vision IP team who last I heard have left for ARM.
I hope they pull it back, as I loved the people there and it had a great culture, but it's been awfully mismanaged for a while and I question how easy it will be to pull it back considering the monopolies and duopolies that are appearing in the semi industry right now.
stn8188 14 hours ago [-]
I don't have nearly the experience with FPGAs that you do, but I really appreciate your comment and insight. Even though I've never used an Altera part on a board, I've always thought that their signal and power integrity documentation was top notch. I can echo the same thing you did: if I need performance, I go with Xilinx; if I need low power glue logic, it's Lattice all the way. Your statement about Lattice in server racks is probably why their acquisition of AMI was a smart move.
duskwuff 9 hours ago [-]
> For Altera, Agilex 9 (ADC and DAC converters integrated with an SoC FPGA) is probably their most interesting device, but that customer base is limited - basically comms and maybe radar with some weird and wonderful optical or quantum compute applications.
They're also competing with AMD's Zynq RFSoC line. I don't know how the two compare from a technology perspective, but AMD has a lot more mindshare.
Aromasin 6 hours ago [-]
Reiterating that my RF knowledge is limited, but they're different classes of devices. Zynq US+ RFSoC at fastest speed grade is only ~6Gsamples/sec, ~7GHz bandwidth RF-ADCs. Agilex 9 is 8 channels of 64 Gsps ADC/DAC.
You want to be comparing it with Versal RF. Agilex 9 has about twice the bandwidth per channel, and keeps all the DSP in the fabric rather than hard blocks. Seems like it has very wide, instantaneous bandwidth and freq range in Ka-band. A few of my colleagues have jumped into startups building optical networking devices around them.
jpgvm 20 hours ago [-]
Hopefully the hard NOC is good this time around. The limitations of the previous series made it mostly useless.
smallmancontrov 11 hours ago [-]
I've been out of the FPGA scene for a while, is the big idea of hard NoC that you can use network/packet abstractions to send data between larger subcomponents as opposed to routing through FPGA fabric and sweating the buffers/timing yourself?
jpgvm 6 hours ago [-]
Yeah, basically instead of consuming registers (or HyperRegisters when it's able to move them into the routing fabric during HyperRetiming) the NoC can be used to connect the main hard IPs to logic on the fabric without necessarily having to locate that logic directly near the pins.
On recent Agilex 7 the NoC exists but is fairly primitive and can only be used for DDR (and maybe HBM?) and it adds latency over direct pin access and has some other downsides that escape my memory right now.
The AMD FPGAs on the other hand have a very powerful and flexible NoC that runs both vertically and horizontally across the die and can be used to not just connect to hard IPs but also user logic across the die.
My hope is this new NoC is much more like AMD implementation, even if it can only do stuff like: Hard IP => Fabric => Hard IP as long as you can use it to connect F-Tile/R-Tile and not just DRAM that will be huge already in terms of saving massive amounts of fabric that otherwise gets eaten up by huge busses.
snvzz 21 hours ago [-]
Likely shipping w/o the proper documentation to enable nextpnr and similar tools, as it's tradition in altera.
I will always choose the vendors that do things properly, when they're even an option.
supaflybanzai 21 hours ago [-]
Like which ones? Honest question.
IshKebab 20 hours ago [-]
There aren't any open commercial FPGAs as far as I know. Some have had their bitstream formats reverse engineered though.
> Not many options unfortunately. Today that's GateMate.
And that's not a great option, frankly. GateMate is a strange design with major performance issues, like the lack of a dedicated clock network.
snvzz 7 hours ago [-]
Good old iCE40 and ECP5, then.
jauntywundrkind 13 hours ago [-]
It's a bit crazy that the LLM / reverse anything age doesn't seem to have hit FPGA world much. I guess not a lot of folks super eager to play with their $10k++++ devices.
aseipp 10 hours ago [-]
You can buy Agilex devices for like $100 now. They're Altera's primary chip family at this point in every device range. You can also use Quartus for free on these devices and even download it all through Docker. Knock yourself out.
The reality is just that it's a lot of work, and Agilex is probably an order of magnitude (or two orders) more complex in scope than any existing FPGA with reversed or open specs. It's going to require a lot of expertise even with superhuman assistance. Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience. If people are going to Claude shit out in the EDA space I'd frankly rather have them work on more important day to day mundane things that are still lacking but important, eg improved performance, power analysis/floorplanning, sdc/constraint based clock synthesis and related tools, etc.
And yes, breaking your device is also a risk for some features too (eg Lattice ECP5 bitstream encryption has never been RE'd since it requires blowing fuses.) But the actual problem requires far more expertise than having Claude reverse engineer gameboy games.
duskwuff 9 hours ago [-]
> Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience.
The terrible Fmax on GateMate is specifically a result of its "quirky" design. There's no dedicated clock network on the part - clocks have to be routed through fabric just like everything else. Running those signals everywhere consumes routing capacity and incurs delays; the resulting clock skew is awful.
omegaSigma95 20 hours ago [-]
[flagged]
logicallee 20 hours ago [-]
Fantastic chip, I love everything about this announcement.
That's not even a paper launch at this stage.
My old perception was still based on pre AMD Xilinx era from 4-5 years ago and Xilinx was basically winning 60-70% market shares as Intel Altera was no where near competitive. ( As usual with any Intel acquisition)
They restricted wage growth too much for too long under Intel (despite being the only growing business unit), so the people with the valuable experience moved elsewhere. The Agilex line-up finally looks to be in the place it should have been 3 years ago, and it seems like they brought in a good marketing team following the Silverlake acquisition, but they still fall in this weird middle-ground now selling "performance-per-watt", which is a hard sell when most engineers optimise for the extremes. If I'm just need a bridge or some glue-logic, I don't need a device which will singe my thumbprints off while doing that. Generally, if you want better performance, AMD does an excellent job, or if you need low power consumption, Lattice is like 4 or 5x lower or more with just enough fmax and IO to be dangerous. If you look read Lattice's shareholder briefings, they're running away with the low/mid-range devices up to ~500k LUTs, and AMD is dominating anything 1M+. I couldn't help but laugh the other day when I saw an Intel reference design with a Lattice MachXO5-NX on it. Look at pretty much any datacentre rack now, and you'll spot 4-64 Lattice devices, when it used to be MAX10s top to bottom. Everything else is swept up by AMD.
For Altera, Agilex 9 (ADC and DAC converters integrated with an SoC FPGA) is probably their most interesting device, but that customer base is limited - basically comms and maybe radar with some weird and wonderful optical or quantum compute applications. I've heard friends of mine in the industry say very good things about it, but RF is not my strength so I can't comment.
In all honesty, they've got an insane fight on their hands to regain the market share. They canned their low end road-map when Sandra Riviera came in (as a classic Intel VP would do) and put all their eggs in the Agilex 7 basket for a long time. They've got Agilex 5 now (and Agilex 3, which is just the bottom SKUs of 5 with it painted over by marketing to fill the gap), which is great for vision applications, but only because they had a fantastic video and vision IP team who last I heard have left for ARM.
I hope they pull it back, as I loved the people there and it had a great culture, but it's been awfully mismanaged for a while and I question how easy it will be to pull it back considering the monopolies and duopolies that are appearing in the semi industry right now.
They're also competing with AMD's Zynq RFSoC line. I don't know how the two compare from a technology perspective, but AMD has a lot more mindshare.
You want to be comparing it with Versal RF. Agilex 9 has about twice the bandwidth per channel, and keeps all the DSP in the fabric rather than hard blocks. Seems like it has very wide, instantaneous bandwidth and freq range in Ka-band. A few of my colleagues have jumped into startups building optical networking devices around them.
On recent Agilex 7 the NoC exists but is fairly primitive and can only be used for DDR (and maybe HBM?) and it adds latency over direct pin access and has some other downsides that escape my memory right now.
The AMD FPGAs on the other hand have a very powerful and flexible NoC that runs both vertically and horizontally across the die and can be used to not just connect to hard IPs but also user logic across the die.
My hope is this new NoC is much more like AMD implementation, even if it can only do stuff like: Hard IP => Fabric => Hard IP as long as you can use it to connect F-Tile/R-Tile and not just DRAM that will be huge already in terms of saving massive amounts of fabric that otherwise gets eaten up by huge busses.
I will always choose the vendors that do things properly, when they're even an option.
We're starting to see open source FPGAs but they are miniscule: https://tinytapeout.com/chips/ttihp26a/tt_um_fabulous_ihp_26...
Next best thing? The mature reverse-engineered families nextpnr[0] supports.
0. https://github.com/YosysHQ/nextpnrhttps://github.com/YosysHQ...
And that's not a great option, frankly. GateMate is a strange design with major performance issues, like the lack of a dedicated clock network.
The reality is just that it's a lot of work, and Agilex is probably an order of magnitude (or two orders) more complex in scope than any existing FPGA with reversed or open specs. It's going to require a lot of expertise even with superhuman assistance. Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience. If people are going to Claude shit out in the EDA space I'd frankly rather have them work on more important day to day mundane things that are still lacking but important, eg improved performance, power analysis/floorplanning, sdc/constraint based clock synthesis and related tools, etc.
And yes, breaking your device is also a risk for some features too (eg Lattice ECP5 bitstream encryption has never been RE'd since it requires blowing fuses.) But the actual problem requires far more expertise than having Claude reverse engineer gameboy games.
The terrible Fmax on GateMate is specifically a result of its "quirky" design. There's no dedicated clock network on the part - clocks have to be routed through fabric just like everything else. Running those signals everywhere consumes routing capacity and incurs delays; the resulting clock skew is awful.